1. Field of the Invention
The present invention generally relates to a method of locally forming metal silicide layers, and in particular to a method of locally forming metal silicide layers and avoiding a leakage current between memory cells caused by unwanted metal silicides.
2. Description of the Prior Art
In order to reduce the resistance and improve the performance of an integral circuit, a metal silicide layer, such as titanium silicide, is usually deposited upon the surface of the circuit and elements. But in some regions where the resistance has to be kept high, such as the spaced region between two neighboring memory cells on the same word line, the metal silicide layer should be avoided. A conventional method is shown in FIG. 1: first, a silicon substrate 100 is provided. There are at least two regions on the substrate 100: one is an array region 101, the other is a peripheral region 102. In the array region 101, a dielectric layer 105, such as an oxide-nitride-oxide (ONO) layer, is deposited on the substrate 100. A memory array with gates 110 and sidewalls 130 is formed on the dielectric layer 105, wherein a first spaced region 106 exists between two neighboring memory cells on the same word line. In the peripheral region 102, there""s at least a plurality of gates 120 of transistors and the sidewalls 140 of the gates 120, wherein a second spaced region 107 exists between two neighboring transistors. After a process of forming metal silicide, the metal silicide layers (150,160,170) are formed on the top surface of gates 110 of memory cells, the top surface of gates 120 of transistors, and the surface of silicon substrate 100.
However, within the prior method the process for forming the sidewall 130 of gates 100 of the memory cells is hard to control, so an overetching phenomenon frequently occurs to expose a part of the substrate 100 within the first spaced region 206, as shown in FIG. 2A. Thus a metal silicide layer 240 is also formed on the surface of silicon substrate 100 within the first spaced region 206 when the process of forming metal silicide is carried out. As shown in FIG. 2B, the metal silicide layer 240 on the surface of silicon substrate 100 within the first spaced region 206 will cause the leakage current, and degrade the performance of the memory cells.
It is an object of the invention to provide a method for locally forming metal silicide layers on an integral circuit.
It is another object of the invention to provide a method to avoid a leakage current caused by the formation of metal silicide layers between memory cells on the same word line.
According to the foregoing objects, the present invention provides a method comprising the following steps: first, a silicon substrate is provided. The silicon substrate can be divided into at least two regions: one is the array region, the other is the periphery region. In the array region, an ONO layer is deposited on the substrate, and a plurality of first transistors, such as a memory array, is formed on the ONO layer. A first spaced region exists between any two neighboring transistors of the plurality of the first transistors. In the peripheral region, a plurality of second transistors is formed on the substrate, and a second spaced region exists between any two neighboring transistors of the plurality of the second transistors. The second spaced region is larger than the first spaced region. Afterward, a nitride layer is conformally deposited to cover the surface of the substrate, the array region, the plurality of the first transistors, the peripheral region, and the plurality of the second transistors. Then, an etching step is performed to form the sidewall of the plurality of the first transistors and the sidewall of the plurality of the second transistors. The first spaced region between two neighboring first transistors is therefore reduced and becomes a third spaced region, similarly, the second spaced region between two neighboring second transistors is also reduced to become a fourth spaced region. However the width of the third spaced region remains smaller than that of the fourth spaced region. Afterward, a first silicon oxide layer is conformally deposited to cover the overall array region and the overall peripheral region. Then, an ion implantation is performed to form the sources and drains of the plurality of the first transistors and the plurality of the second transistors. After the ion implantation process, an extra step of rapid thermal process (RTP) may be performed. Then, a second silicon oxide layer is deposited on the first silicon oxide layer. A selective etching process is then performed to remove a part of the first silicon oxide layer and a part of the second silicon oxide layer, so that the top surface of gates of the plurality of the first transistors and the plurality of the second transistors is exposed. However, the silicon oxide layer within the third spaced region remains to avoid exposing the surface of the substrate. A photoresist layer is then formed to cover the overall array region and the overall peripheral region. The part of the photoresist layer within the peripheral region is then removed. By using the remaining photoresist layer as a mask, another etching process is performed to completely remove the oxide layer within the peripheral region. Afterward, the remaining photoresist layer is removed; a metal layer is then deposited to cover the silicon substrate, the array region and the peripheral region. A heating process is then executed to form metal silicide. Finally, the metal layer is removed.